1. Field of the Invention
The invention relates to semiconductor fabrication processes, and more particularly, to a process for fabricating metal-oxide semiconductor (MOS) transistors based on lightly doped drain (LDD) structure.
2. Description of Prior Art
Metal-oxide semiconductor (MOS) transistors are essentially composed of a gate oxide layer, a gate, and an ion-implanted source/drain. A conventional method for increasing the packing density of a MOS transistor IC chip is to shorten the channel in the MOS transistor so as to reduce its feature size. This method, however, can lead to the following two adverse effects: a short channel effect and a hot electrons effect.
The short channel effect arises due to the formation of a depletion layer in the source/drain region during operation of the MOS transistor. The depletion layer overlaps with the channel, thus shortening the effective length of the channel. As a consequence, the subthreshold current is increased due to an increased number of electrons moving from the source through the channel, and the threshold voltage of the MOS transistor is lowered. When the subthreshold is lowered, the gate voltage gradually loses its control of the drain current.
The hot electrons effect arises due to an increase in the transverse electric field intensity across the channel when the channel is shortened, thus allowing the electrons near the drain to gain acceleration to an energy level higher that under thermal equilibrium. These high energy electrons are thus referred to as "hot electrons". The carrier multiplication effect arising due to collisions among these hot electrons causes some of the electrons to damage the gate oxide layer and be trapped in the gate, thereby causing the MOS transistor to deteriorate in performance and reliability. The undesired effect of punchthrough can also arise.
In order to attempt to cope with the aforementioned problems of short channel and hot electron effects, lightly doped drain (LDD) structures have been proposed. In this approach, a region near the channel is doped with a concentration lower than the earlier formed N.sup.+ source/drain regions to form a lightly doped N.sup.- region. The provision of the lightly doped N.sup.- region allows a decrease in the transverse electric field intensity, thereby preventing hot electrons from being generated.
FIG. 1 shows a sectional diagram depicting; the structure of the conventional LDD-based MOS transistor, which comprises a silicon substrate 10 on which an active region is defined. Gate oxide layer 11, gate 12, and spacer 14 are then successively formed on the silicon substrate 10. An ion implantation process is performed twice through the spacer 14 so as to form a heavily doped source/drain region 15 and a lightly doped source/drain region 13. The formation of the lightly doped source/drain region 13 thus allows a decrease in the transverse electric field intensity.
One drawback of the aforementioned LDD structure is that, since the source includes a lightly doped N.sup.- region, the resistance thereof is relatively high due to the low concentration of carriers in the lightly doped N.sup.- region. This high resistance causes the series resistance between the drain and the source to be high, thus causing the MOS transistor to deteriorate in performance and to have more electric power dissipation. In other words, the channel current in the source region is inoperable under low voltage.